This invention relates generally to semiconductor packages and to modules having such packages.
As is known in the art, semiconductor packing is typically performed by forming a plurality of identical integrated circuit chips on a semiconductor wafer. Also formed on the wafer during the fabrication of the chips is a plurality of scribe lines, or kerfs, which separate the chips. The integrated circuit chip definition is essentially complete at this wafer processing level. Some modification using electrical or laser fusing is possible such as spare, or redundant element replacement and circuit parameter (e.g., resistance) trimming, but this is limited to electrical elements with a single chip.
The wafer is then tested. The individual chips are then diced (i.e., separated) by scribing and breaking along the scribe lines. The now separated chips are individually packaged, re-tested, and sold as individual packaged chips. Typically, these individually packaged chips are mounted to a printed circuit board (PCB). For example, when the chips are Dynamic Random Access Memories (DRAMs), the individual packaged chips are mounted to a PCB to provide a memory module, such as a Single In-Line Memory Module (SIMM), Dual In-Line Memory Module (DIMM), or Rambus In-Line Memory Module (RIMM).
As is also known in the art, a DRAM chip typically includes two regions: memory array regions; and, non-memory array regions. These non-memory array regions are generally referred to as regions peripheral to the array regions or merely as peripheral regions. More particularly, referring to FIG. 1, a semiconductor wafer 10 is shown having a plurality of identical semiconductor chips 12. The fabricated chips 12 are then separated along the scribe lines 14. The borders of the scribe lines 14 are shown more clearly in FIG. 2 and are designated as 14a, 14b, such as FIG. 2 showing a portion of the wafer 10 shown in FIG. 1. Thus, an exemplary one of the chips 12 is shown in detail in FIG. 2 to include memory array regions, here four memory array regions 16 and peripheral regions 17. Each array region 16 includes the DRAM memory cells and associated row and column decoders, not shown. The peripheral regions 17 typically include decoders and sense amplifiers, not shown. Also included in the peripheral region 17 of each chip 12 is, in this example, a pair of voltage generators 20. Also disposed in the peripheral regions 17 are power busses 22 which electrically interconnect the voltage generators 20 to the array regions 16. In a conventional DRAM semiconductor chips, the voltage generators 20 occupy up to several percent of the total chip 12.